Optimized CMOS Design of Full Adder using 45nm Technology
نویسندگان
چکیده
منابع مشابه
Design of Low Power Reduced Wallace Multiplier with Compact Carry Select Adder, Half Adder & Full Adder Using Cmos Technology
The Wallace Multiplier is mainly used in the Arithmetic & Logic Unit (ALU) to perform the scientific computation in processors, controller etc... The existing multiplication technique like booth multiplier, array multiplier etc requires more time in multiplications. Hence Wallace Multiplier has been designed by using the parallel process to reduce the delay. The regular Wallace Multiplier requi...
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ژورنال
عنوان ژورنال: International Journal of Computer Applications
سال: 2016
ISSN: 0975-8887
DOI: 10.5120/ijca2016909978